Cadence analysis

EM/IR analysisPAC/PSS analysis

CADENCE VIRTUOSO TRICKS

How to display Verilog-A model parameters in Cadence Virtuoso?How to get rid of solder dot warning (intersection of 4 wires) in Cadence Virtuoso?How to make wires thicker in Cadence Virtuoso?How to renumber instances in Cadence Virtuoso?Net naming tricks in Cadence VirtuosoUseful hotkeys Cadence Virtuoso

Design Presentation

3D Layout Viewer

Layout

IC Layout BasicsLayout editor settings and tricksLayout-Dependent EffectsMatching in layout

MATLAB scripts

RLC-calculator for PCB trace

Simulation Hacks

Simulation Hacks

SKILL language

Extracting Library and Cell Names from a Top Cell Hierarchy Using SKILL CodeSetting Up SKILL IDE in Cadence Virtuoso Environment

Useful materials

Layout Design MaterialsPrintable CheatsheetsSchematic Design Materials

VERILOG-A MODELS

Analog-to-Digital Converter (ADC) Verilog-A model (any resolution)Binary Counter Verilog-A modelBinary to Thermometer Encoder Verilog-A modelComparator Verilog-A modelDecimal to Binary Encoder Verilog-A modelDecimal to Thermometer Encoder Verilog-A modelDigital-to-Analog Converter (DAC) Verilog-A model (any resolution)High-pass filter (HPF) Verilog-A modelLevel shifter Verilog-A modelLow-pass filter (LPF) Verilog-A modelNon-overlapping clock generator Verilog-A modelPWM generator Verilog-A modelVerilog-A block for saving simulation results to fileVoltage-controlled oscillator (VCO) Verilog-A model