Matching patterns in layout

Table of Contents

1. Introduction
2. Matching principles
3. Matching patterns
4. Interdigitation
5. Common Centroid
6. Matching guide

1. Introduction

In the previous article we spoke about the matching theory in analog layout. In this article we will dive deeper into matching patterns, such as Interdigitation and Common Centroid and how to create your own matching pattern in layout. We will also discuss some practical aspects of matching.

2. Matching principles

While creating a layout pattern we should follow a few simple, but important rules that will ensure that our array provides a proper matching to every device and neutralises negative effects, ensuring the best possible performance of the circuit. Here are the rules:

1. Geometry – Every segment of the array should be unit-sized and have the same geometry; Orientation of all devices should be the same;

2. Symmetry – Array segments should be placed symmetrically for both X- and Y-axes;

3. Compactness – The array should be as compact as possible, ideally square-shaped;

4. Distribution – Array segments should be distributed as evenly as possible;

5. Positioning – Matched array should be placed as far as possible from potential aggressors (high current/frequency blocks etc.)

6. Edging – Array segments should be surrounded by dummies to ensure equal edge conditions for core devices and protect from layout-dependent effects.

3. Matching Patterns

The main goal of matching is to achieve an equal impact of non-idealities in CMOS process for the critical structures, such as differential pairs and current sources. There are plenty of factors that are playing against precision of the device manufacturing - temperature, dopants, etc. gradients. We cannot eliminate those gradients from the manufacturing process, right?

Instead, we can fight against those effects in layout by distributing the critical devices in the way that every device sees the same impact and will cancel it, just as differential signalling. There are two main types of matching patterns in layout - Interdigitation and Common Centroid. Let's walk through them and understand each other's application.

Matching patterns

4. Interdigitation

Interdigitation - is the simplest way of matching a circuit. This pattern is suitable for the simple current mirrors, voltage dividers (resistive or capacitive) and simple biasing circuits. Interdigitation provides good matching properties against 1D-gradients and is suitable for the simple circuits. The main concept is that you should create an imaginary center line and place your devices symmetrically, relative to this line. The simplest example of that is so called "ABBA" pattern:

The classics of matching - the "ABBA" pattern

Let's compare an unmatched array and an interdigitated array by applying a simple 1D gradient to both structures:

Applying a gradient for the devices

Now, let's count the impact for each device:

Unmatched:

$$A = 1 + 2 = 3$$ $$B = 3 + 4 = 7$$

That's a huge difference, isn't it? Imagine those devices being your input differential pair - this would cause a wild offset due to the unsymmetry of those devices!

ABBA pattern:

$$A = 1 + 4 = 5$$ $$B = 2 + 3 = 5$$

... meaning that both devices are seeing the same impact!

We can apply the same principle (centerline symmetry) even if we have more devices:

Interdigitation pattern for 4A and 24 devices

Even if we have more devices, the principle stays the same. Here is the example of 8A, 4B and 4C devices:

Interdigitation pattern for 8A-4B-4C array

To check that our pattern is still correct, we can apply the same procedure, as in our first ABBA example:

Interdigitation gradient for 8A-4B-4C array

Applying a linear gradient to all devices and calculating the impact for each segment, we get:

$$A = 1 + 2 + 3 +4 +5 +6+7+8 =36$$ $$B = 2 + 3 +6+7= 18$$ $$C = 1 + 4 +5+8=18$$

Taking into account that $A = 2B = 2C$, we can see that all devices in this array are seeing the same impact from 1D gradient applied.

Interdigitation matching procedure:

1. Make sure the smallest device has at least 2 multipliers and 2 fingers (in case of MOS device);
2. Each device has the same finger width and length. Use multipliers to achieve the required total width;
3. Place the smallest device in the center of the pattern;
4. Keep adding devices on the left and on the right, starting from the smallest devices.

The following tutorial shows how to create an interdigitation pattern for a current mirror in Cadence Layout GXL:

5. Common Centroid

Common Centroid is more advanced matching technique, suitable for more complex analog structures, such as differential pairs, BJT arrays in Bandgaps, R/C DAC array etc. The difference between interdigitation and common centroid is that common centroid provides better matching for 2D gradients, which is critical for the large arrays and advanced (below 28nm) nodes.

The main idea behind common centroid is that we make our array symmetrical of the common centre. In other words, the array should be symmetrical in both X- and Y- axes.

Let's dive in through an example - a complex current mirror that has 2A, 4B and 8C devices:

Current mirror example

The first step would be to draw an imaginary symmetry lines for X- and Y- axes. Then, we will place the smallest device on the first diagonal, as shown below:

Place the smallest device on diagonal

Then, take the next smallest device (B) and place two multipliers on the opposite diagonal:

Place next device on the opposite diagonal

Repeat the process, moving from the smallest to the largest device, placing 2 devices on one diagonal at a time:

Keep placing the devices interleaving the diagonals

Now we have two possible options how to place segment of the device $C$:

Let's fill the remaining segments of $C$:

And add dummies to complete the pattern:

Now, let's verify our patterns and check if it works as a matched array. We will follow the same procedure as for interdigitation pattern, but apply the gradient in two directions as shown below:

Applying 2D gradient to both arrays

The total impact for each segment will be defined as a sum of gradient for $X$ and $Y$ axes. For example, for the first array, the impact for the first $A$ segment will be:

$$A_1 = 3+2$$

And for the second array:

$$A_2 = 2+3$$

Detailed impact calculation

First array: $$A = A_1 + A_2 = (3+2) +(2+3) = 10$$ $$B = B_1 +B_2+B_3+B_4=(3+1)+(2+2)+(3+3)+(2+4) = 20$$ $$C = C_1 +C_2+C_3+C_4+C_5+C_6+C_7+C_8 = (4+1)+(4+2)+(4+3)+(3+4)+(2+1)+(1+2)+(1+3)+(1+4) = 40$$

Second array:

$$A = A_1 + A_2 = (3+2) +(2+3) = 10$$ $$B = B_1 +B_2+B_3+B_4=(3+1)+(2+2)+(3+3)+(2+4) = 20$$ $$C = C_1 +C_2+C_3+C_4+C_5+C_6+C_7+C_8 = (4+1)+(4+2)+(4+3)+(4+4)+(1+1)+(1+2)+(1+3)+(1+4) = 40$$

Note: Even though devices in both arrays are facing the same impact, the second array would be more preferable, because it exhibits better distribution of the $C$ devices within the array.

Common Centroid matching procedure:

1. Make sure all devices are unit-sized;
2. Make sure every device has at least 2 fingers and 2 multipliers;
3. Assign one letter to each device and count its multipliers;
4. Draw a vertical and horizontal axis; the intersection would be the center of our array;
5. Imagine two diagonal cuts, $D_1$ and $D_2$;
6. Take the smallest device and place two multipliers in the center on $D_1$; if this device has more than 2 multipliers, place them too, but on $D_2$

The following tutorial shows how to create a common centroid pattern for a differential pair in Cadence Layout GXL:

6. Matching guide

So, we've learned two main matching patterns and how to implement and check them in layout. You might ask a reasonable question - How to select a suitable matching pattern for an analog structure? The answer is quite simple - the Interdigitation is a less complex method, and it would be sufficient for structures like small current mirrors and biasing circuits. Using this pattern will be more area-efficient and allows simple routing.

When we are talking about structures that require maximum precision - such as R/C DAC arrays, differential pairs - we have to use the Common Centroid to achieve the best performance. The typical analog structures and the corresponding matching patterns are summarized in the table below:

Summarizing the things we discussed above we can come up with a generic matching procedure, listed below.

Matching procedure:

1. Define the purpose and type of the structure (current mirror/diff. pair etc.)
2. Define the type of matching required (interdigitation/common centroid)
3. Check/select unit element sizing:

3a. NMOS/PMOS transistors:

- All devices have the same length

- Minimum-sized device has at least 2 fingers and (if possible) 2 multipliers

- Other devices have at least 2 fingers

3b. Capacitive/resistive arrays:

- All devices are multiples of the unit-sized device

3c. BJT arrays:

- All devices are multiples of the unit-sized device

4. Shape an array as close as possible to the square
5. Estimate main routing lines and reserve space for them between array elements
6. Apply proper matching pattern to the array
7. Surround the array with dummies and adjust their size for area efficiency
8. Place the guard ring and add a PWELL/NWELL layer
9. Combine N+/P+ areas to avoid spacing DRCs.