Matching in layout

Introduction
Matching techniques
Placement
Dummies

1. Introduction

Matching - is a very important technique in Analog IC layout. It helps compensating a lot of undesirable layout-dependent effects. In IC design there are multiple sources of nonidealities that affecting IC performance. We can split them into two categories: manufacturing-related and environmental. Manufacturing-related sources includes dopant gradients, oxide thickness gradients, and mechanical stress, which are very hard to predict and simulate. Environmental factors includes temperature gradients which is also hard to predict.

Gradient types

There are two main types of mismatch: systematic and random mismatch.

Mismatch types

Mismatch compensation techniques

2. Matching Techniques

Matching - is a very useful technique in IC layout targeting similar performance from every device in analog design. Let's take a look on a very simple example - a current mirror (1:2). Reference current $I_{ref}$ is copied from device A (2 fingers, 2 multipliers) to the device B (2 fingers, 4 multipliers) producing an output current $I_{out}=2I_{ref}$ . For a current mirror to exhibit a good performance it is required that both devices A&B have the same performance. First, let's have a look on the placement without matching and apply a linear gradient to it:

Gradient impact on unmatched devices

Now we can summarize the total impact on the each devices:
$A = 1 + 2 = 3$

$B = 3 + 4 + 5 + 6 = 18$

Keeping in mind that the device B is 2 times larger than device A:

$[A = 3] < [B = 9]$

We can clearly see, that the impact of the linear gradient on the device B is 3 times larger than on the device A. It means that if we have any gradient on this current mirror (i.e. dopants gradient), device B will have, for example, a different $V_{th}$ , and this will negatively affect the accuracy of the current mirror circuit.

Let's now apply an interdigitation pattern to our devices. In order to have a symmetry in our placement, we should implement a $BBAABB$ pattern:

Gradient impact on the matched devices

In this case, the total impact on each device:
$A = 3 + 4 = 7$

$B = 1 + 2 + 5 + 6 = 14$

Keeping in mind that the device B is 2 times larger than device A:

$[A = 7] = [B = 7]$

We can clearly see, that the impact of the linear gradient on both devices is equal and will not affect the accuracy of the circuit. Now, let's take a 2-dimensional example and see, how dummies together with matching help us to achieve the best performance.

Let's say we have the same circuit - a simple current mirror (1:2) that is using a *Common centroid technique and surrounded by dummies. If we apply a linear gradient to this structure, devices will stay matched, as in the previous example (red gradient):

Gradient impact on the matched devices

Another effect, that we want to take into account here is the WPE effect. This effect impacts devices, placed close to the well edge (blue gradient):

Gradient impact on the matched devices

By surrounding our core devices with dummy devices around, we are achieving two main things:

Allowing sufficient distance for the core devices from the well edge to prevent WPE impact;
Creating equal edge conditions for core devices to reduce mask effects.

Gradient and WPE impact on the matched devices

3. Placement

Correct placement of the devices is playing a vital role in layout. Placing devices aas evenly as possible will reduce a lot of unwanted effects. Let's have a look on the placement examples and discuss their impact on the design.

Examples of the wrong placement

For the first example on the image above, we can see that two devices has a different orientation. This will lead to a variation in device parameters due to gradients that are going along the different axis of symmetry. It worth mentioning that it is always recommended to keep gate orientation same for all the devices in the design, and for more advanced technologies (28nm and below) it is mandatory. The second example shows two devices with different widths. In this case, the main problem is the different size of the masks that will lead to different edge-effects for each device. The third example shows two devices with a different lengths. Those devices will also have a different size masks, affecting the performance in the same way as in a previous example.

We should also be aware of not only the shape and orientation of the matched devices themselves, but also about the surrondings. ASIC are usually contain sensitive analog blocks, such as amplifiers, bandgaps and comparators together with a noisy or high-current blocks, such as LDOs, drivers and digital logic. Those blocks may create a lot of substrate noise and temperature gradients, that may impact the performance of the sensitive devices.

Examples of the wrong placement in respect of the agressor

As shown in the example above, in the first case, the location of the matched devices with respect to the agressor is incorrect, because the gradient, caused by the agressor is affecting both devices unequally. In the second case, both devices are located symmetrically to the agressor, hereby reducing and equalising the stress on the sensitive devices.

4. Dummies

As we discussed previously, dummy devices are very useful in preventing layout-dependent effects and protecting the core devices. However, we have to be careful while placing the dummies, because they may cause unwanted parasitics. Basically, in layout we can place matched devices with spacing or abut them. Abutting the matched devices has a lot of benefits, such as reduction in parasitic capacitance and resistance. Let's have a look on the matched structure with spacing:

Spaced dummy placement

In this case, all our devices are equally spaced and all terminals of the dummy devices are shorted and connected to the substrate potential (ground for NMOS and power for PMOS devices). As soon as all terminals of the dummy device are shorted, we don't have any extra parasitics.

Abutted dummy placement

If we want to abut our core devices together, we have to abut them with ddummy devices to achieve equal edge effects for core devices. In this example, devices A & B are sharing source terminals connected to the ground while abutting. SO, after abutting of the core devices, the only possible connection for the dummies is $I_{out}$ termanal. In this case, drain, source and gate of the dummy will be connected to the $I_{out}$ whereas the bulk terminal will remain connected to the ground. This will create a MOS capacitor structure, where one terminal is connected to the ground and the other is connected to $I_{out}$ , utilizing the $C_{SB}$ of the dummy device. This parasitic capacitance is connected to the drain terminal of the device B, which will cause extra loading and reduction in speed. Such connection of the dummy devices will be even more critial for the structures like differential pair, where parasitic capacitance will not ony cause the loading and bandwidth reduction, but can even unbalance the circuit and lead to an increased offset.

Dummy key points:

Dummy placement style follows the core device placement (sapced or abutted);

Spaced placement doesn't add parasitics but lacks the benefit of the parasitics reduction;

Abutted placement reduces core devices resistance and capacitance, but suffers from the dummy $C_{SB}$ parasitics;

Matching summary

Matching methodology