ADC

This article contains Verilog-A model for saving simulation results to .txt file.

Usage:

1. Create a new cell in Library Manager named save2file and select cell type Verilog A;
2. Copy and paste the code provided;
3. Modify path variable to define the path to the output text file;
4. Perform Check and Save;
5. A cell symbol will be created;
6. Instantiate save2file cell into your design;
7. Perform Check and Save and run the simulation.

Cell name: save2file

Model type: Verilog-A

1// Verilog-A file for saving sim data to .txt
2// Authors: I.Smirnov,  M.Gaidukov
3// Source: AnalogHub.ie
4
5`include "constants.vams"
6`include "disciplines.vams"
7
8module save2file(smp,in);
9input smp, in;
10voltage smp, in;
11
12parameter real vdd = 1;
13parameter real vth = vdd/2;
14parameter real montecarlo = 0;
15parameter string file_nm = "idle";
16parameter string path = "";                     // "YOUR_PATH/FILENAME.txt"
17
18integer fp = 0;
19integer file_number;
20string file_number_str;
21analog begin
22  @(initial_step) begin
23    if (montecarlo > 0.5) begin
24      file_number = {$random} % 1000;
25      $sformat(file_number_str,"%d",file_number);
26      fp = $fopen({path,file_nm,"_mc_",file_number_str,".txt"},"w");
27    end
28    else begin
29//      $sformat(file_nm_string,"%d",file_nm);
30      fp = $fopen({path,file_nm,".txt"},"w");
31    end
32  end
33  @(cross(V(smp)-vth,+1)) begin
34    $fwrite(fp,"%e ",V(in));
35    $fwrite(fp,"\n");
36  end
37end
38endmodule

Authors: I. Smirnov, M. Gaidukov