Non-overlapping clock generator

This article contains Verilog-A models for a Non-overlapping clock generator.

Table of Contents

1. Non-overlap clock generator (same as clk)
2. Non-overlap clock generator with 2 phases
3. Non-overlap clock generator with 4 phases

Usage:

1. Create a new cell in Library Manager named nonoverlap_clk and select cell type Verilog A;
2. Copy and paste the code provided;
3. Specify vdd and vss variables to reflect high/low levels of the clk;
4. Specify t_edge and t_delay variables to be the rising/falling time and delay of the output waveform;
5. Specify t_dead to define the dead time between phases;
6. Perform Check and Save;
7. A cell symbol will be created;
8. Instantiate nonoverlap_clk cell into your design;
9. Perform Check and Save and run the simulation.

Non-overlapping clock generator (same as clk)

Nonoverlap_clk testbench

Nonoverlap_clk simulation result

Cell name: nonoverlap_clk

Model type: Verilog-A

1 
2// Non-overlap clock generator (same freq as clk)
3// Author: A. Sidun
4// Source: AnalogHub.ie
5
6`include "constants.vams"
7`include "disciplines.vams"
8
9module nonoverlap_clk (clk, ph1, ph2);
10    input clk;
11    output ph1, ph2;
12    electrical clk, ph1, ph2;
13
14    parameter real vdd = 5.0;		// define clock high
15    parameter real vss = 0.0;		// define clock low
16    parameter real t_edge = 1e-9;	// rising/falling edge of ph1/ph2
17    parameter real t_delay = 1e-9;	// delay from the input clock edge for ph1/ph2
18    parameter real t_dead = 20e-9; 	// dead-time between ph1/ph2
19
20    real delay_ph1;
21    real delay_ph2;
22    real d_ph1;
23    real d_ph2;
24
25analog begin
26@(initial_step) begin
27    d_ph1 = 1;
28    d_ph2 = 0;
29    end
30
31@(cross(V(clk)-vdd/2, +1)) begin	//rising edge of clk
32        d_ph1 = 1;
33        d_ph2 = 0;
34		delay_ph1 = t_delay + t_dead;
35		delay_ph2 = t_delay;
36end
37
38@(cross(V(clk)-vdd/2, -1)) begin	//falling edge of clk
39        d_ph1 = 0;
40        d_ph2 = 1;
41		delay_ph1 = t_delay;
42		delay_ph2 = t_delay + t_dead;
43end
44
45V(ph1) <+ vdd*transition(d_ph1,delay_ph1,t_edge) + vss*transition(d_ph2,delay_ph1,t_edge);
46V(ph2) <+ vdd*transition(d_ph2,delay_ph2,t_edge) + vss*transition(d_ph1,delay_ph2,t_edge);
47
48end //analog begin
49endmodule

Non-overlapping clock generator with 2 phases

2-phases nonoverlap_clk testbench

2-phases nonoverlap_clk simulation result

Cell name: nonoverlap_clk_2ph

Model type: Verilog-A

1 
2// Non-overlap clock generator (frequency-divided)
3// Author: A. Sidun
4// Source: AnalogHub.ie
5
6`include "constants.vams"
7`include "disciplines.vams"
8
9module nonoverlap_clk_2ph (clk, ph1, ph2);
10    input clk;
11    output ph1, ph2;
12    electrical clk, ph1, ph2;
13
14   	parameter real vdd = 5.0;   // define clock high
15    parameter real vss = 0.0;	// define clock low
16	parameter real t_edge = 1e-9;   // rising/falling edge of ph1/ph2
17	parameter real t_delay = 1e-9;  // delay from the input clock edge for ph1/ph2
18    parameter real t_dead = 20e-9;  // dead-time between ph1/ph2
19
20    real delay_ph1;
21    real delay_ph2;
22    real d_ph1;
23    real d_ph2;
24    integer counter_ph1=0;
25
26analog begin
27@(initial_step) begin
28    d_ph1 = 1;
29    d_ph2 = 0;
30    end
31
32
33@(cross(V(clk)-vdd/2, +1)) begin	//rising edge of clk
34        counter_ph1 = counter_ph1 + 1; // count rising edges
35		$display("Rising edge number: %d", counter_ph1);
36        case(counter_ph1)
37        1: begin
38            d_ph1 = 1;
39            d_ph2 = 0;
40            delay_ph1 = t_delay + t_dead;
41		    delay_ph2 = t_delay;
42        end
43        2: begin 
44            d_ph1 = 0;
45            d_ph2 = 1;
46            delay_ph1 = t_delay;
47		    delay_ph2 = t_delay + t_dead;
48            counter_ph1 = 0;    // reset counter
49        end
50endcase
51end
52
53
54/*@(cross(V(clk)-vdd/2, -1)) begin	//falling edge of clk
55        d_ph1 = 0;
56        d_ph2 = 1;
57		delay_ph1 = t_delay;
58		delay_ph2 = t_delay + t_dead;
59end */
60
61V(ph1) <+ vdd*transition(d_ph1,delay_ph1,t_edge) + vss*transition(d_ph2,delay_ph1,t_edge);
62V(ph2) <+ vdd*transition(d_ph2,delay_ph2,t_edge) + vss*transition(d_ph1,delay_ph2,t_edge);
63
64end //analog begin
65endmodule

Non-overlapping clock generator with 4 phases

4-phases nonoverlap_clk testbench

4-phases nonoverlap_clk simulation result

Cell name: nonoverlap_clk_4ph

Model type: Verilog-A

1 
2// 4-phases non-overlap clock generator 
3// Author: A. Sidun
4// Source: AnalogHub.ie
5
6//               ____      ____      ____      ____      ____      ____
7// CLK      ____|    |____|    |____|    |____|    |____|    |____|    |____
8//               _________                               _________
9// PH1      ____|         |_____________________________|         |_______________  
10//                         _________                               _________                 
11// PH2      ______________|         |_____________________________|         |_______________ 
12//                                   _________                               _________ 
13// PH3      ________________________|         |_____________________________|         |_______________ 
14//                                             _________                               _________ 
15// PH4      __________________________________|         |_____________________________|         |_______________ 
16
17// Non-overlap clock generator (frequency-divided)
18
19`include "constants.vams"
20`include "disciplines.vams"
21
22module nonoverlap_clk_4ph (clk, ph1, ph2, ph3, ph4);
23    input clk;
24    output ph1, ph2, ph3, ph4;
25    electrical clk, ph1, ph2, ph3, ph4;
26
27   	parameter real vdd = 1.0;   // define clock high
28    parameter real vss = 0.0;	// define clock low
29	parameter real t_edge = 1e-9;   // rising/falling edge of ph1/ph2
30	parameter real t_delay = 1e-9;  // delay from the input clock edge for ph1/ph2/ph3/ph4
31    parameter real t_dead = 20e-9;  // dead-time between ph1/ph2/ph3/ph4
32
33    real delay_ph1;
34    real delay_ph2;
35    real delay_ph3;
36    real delay_ph4;
37    real bit_ph1;
38    real bit_ph2;
39    real bit_ph3;
40    real bit_ph4;
41    integer clk_edge_count=0;   // clock rising edge counter
42
43analog begin
44@(initial_step) begin
45    bit_ph1 = 0;
46    bit_ph2 = 0;
47    bit_ph3 = 0;
48    bit_ph4 = 0;
49    end
50
51
52@(cross(V(clk)-vdd/2, +1)) begin	//rising edge of clk
53        clk_edge_count = clk_edge_count + 1; // count rising edges
54		//$display("Rising edge number: %d", clk_edge_count);
55        case(clk_edge_count)
56        1: begin
57            bit_ph1 = 1;
58            bit_ph2 = 0;
59            bit_ph3 = 0;
60            bit_ph4 = 0;
61			delay_ph4 = t_delay;
62            delay_ph1 = t_delay + t_dead;
63        end
64        2: begin 
65            bit_ph1 = 0;
66            bit_ph2 = 1;
67            bit_ph3 = 0;
68            bit_ph4 = 0;
69			delay_ph1 = t_delay;
70		    delay_ph2 = t_delay + t_dead;
71
72        end
73        3: begin 
74            bit_ph1 = 0;
75            bit_ph2 = 0;
76            bit_ph3 = 1;
77            bit_ph4 = 0;
78			delay_ph2 = t_delay;
79			delay_ph3 = t_delay + t_dead;
80
81        end
82        4: begin 
83            bit_ph1 = 0;
84            bit_ph2 = 0;
85            bit_ph3 = 0;
86            bit_ph4 = 1;
87			delay_ph3 = t_delay;
88			delay_ph4 = t_delay + t_dead;
89            clk_edge_count = 0;    // reset counter
90        end
91endcase
92end
93
94V(ph1) <+ vdd*transition(bit_ph1,delay_ph1,t_edge) + vss*transition(bit_ph2,delay_ph1,t_edge);
95V(ph2) <+ vdd*transition(bit_ph2,delay_ph2,t_edge) + vss*transition(bit_ph1,delay_ph2,t_edge);
96V(ph3) <+ vdd*transition(bit_ph3,delay_ph3,t_edge) + vss*transition(bit_ph3,delay_ph3,t_edge);
97V(ph4) <+ vdd*transition(bit_ph4,delay_ph4,t_edge) + vss*transition(bit_ph4,delay_ph4,t_edge);
98
99end //analog begin
100endmodule