Digital Level Shifter
This article contains Verilog-A model for a digital Level Shifter.
Table of Contents
Usage:
- Create a new cell in Library Manager named level_shifter and select cell type Verilog A;
- Copy and paste the code provided;
- Specify input_swing variable to be the output swing;
- Specify t_edge and t_delay variables to be the rising/falling time and delay of the output waveform;
- Perform Check and Save;
- A cell symbol will be created;
- Instantiate level_shifter cell into your design;
- Perform Check and Save and run the simulation.
Cell name: level_shifter
Model type: Verilog-A
1// Digital level shifter (without inversion)
2// Takes differential input - connect your signal to inp, reference to inn
3// Output will be level-shifted to the "low" and "high" levels
4// Author: A. Sidun
5// Source: AnalogHub.ie
6
7`include "constants.vams"
8`include "disciplines.vams"
9
10module level_shifter (inp, inn, outn, outp, low, high);
11 input inp, inn, low, high;
12 output outp, outn;
13 electrical inp, inn, outp, outn, low, high;
14 integer d_outp, d_outn; // logic output state
15
16 parameter real input_swing = 5.0; // define input signal swing
17 parameter real t_edge = 1e-9;
18 parameter real t_delay = 1e-9;
19
20analog begin
21@(initial_step) begin
22 d_outp = 0;
23 d_outn = 1;
24 end
25
26@(cross(V(inp)-V(inn) - 0.5*input_swing,0)) begin
27 if (V(inp)-V(inn)>0.5*input_swing) begin
28 d_outp = 1;
29 d_outn = 0;
30 end
31 else begin
32 d_outp = 0;
33 d_outn = 1;
34end // end if
35
36end // end cross
37
38V(outp) <+ V(high)*transition(d_outp,t_delay,t_edge) + V(low)*transition(d_outn,t_delay,t_edge);
39V(outn) <+ V(high)*transition(d_outn,t_delay,t_edge) + V(low)*transition(d_outp,t_delay,t_edge);
40
41end //analog begin
42endmoduleCell name: level_shifter_inv
Model type: Verilog-A
1
2// Level shifter with inversion (digital)
3// Author: A. Sidun
4// Source: AnalogHub.ie
5
6`include "constants.vams"
7`include "disciplines.vams"
8
9module level_shifter_inv (inp, inn, outn, outp, low, high);
10 input inp, inn, low, high;
11 output outp, outn;
12 electrical inp, inn, outp, outn, low, high;
13 parameter real VDD = 5.0; // Output voltage during high state
14
15analog begin
16
17@(initial_step)
18 V(outp) <+ V(high);
19 V(outn) <+ V(low);
20
21 if ((V(inp)-V(inn)) > VDD/2) begin
22 V(outp) <+ V(high);
23 V(outn) <+ V(low);
24 end
25
26 if ((V(inp)-V(inn)) < VDD/2) begin
27 V(outp) <+ V(low);
28 V(outn) <+ V(high);
29 end
30end
31
32endmodule