2 min readBy

Decimal-to-Binary Encoder

This is a static combinatorial block that converts a fixed decimal value (set via the decimal_number parameter) into a parallel binary output bus — there is no input port and no clock, so the output is driven once at simulation start. It is most useful as a one-shot bit-pattern generator when you need to pre-load a specific digital code into a DAC, decoder, or register model at the beginning of a simulation. The binary_bits macro sets the bus width and vdd/vss define the output logic levels. A typical use-case is quickly applying a known static code to a DAC model to verify its output voltage at a specific operating point, without wiring up a counter or sequencer stimulus.

This page contains Verilog-A model of the decimal to binary encoder.

Usage:

Create a new cell in Library Manager named dec2bin and select cell type Verilog A;
Copy and paste the code provided;
Specify binary_bits variable to be the desired binary bits number;
Perform Check and Save;
A cell symbol will be created;
Instantiate dec2bin cell into your design;
Perform Check and Save and run the simulation.

Cell name: dec2bin

Model type: Verilog-A

verilog

// Decimal number to binary code converter
// LSB is [0]
// Change binary_bits variable for your needs!
// Source: AnalogHub.ie

`include "constants.vams"
`include "disciplines.vams"
`define binary_bits 8				// define number of binary bits here

module dec2bin(out);
output [`binary_bits-1:0] out;
voltage [`binary_bits-1:0] out;

parameter real decimal_number = 5;
parameter real vdd = 1.0;			// voltage level of logic 1 (V)
parameter real vss = 0;				// voltage level of logic 0 (V)
real dout[`binary_bits-1:0];		// internal result variable
genvar i;
real x;
real z;

analog begin
// Converting decimal to binary using modulus of 2
	x = decimal_number;
while (x!=0) begin
	for (i = 0; i <`binary_bits; i = i + 1) begin
		z = x/2.0;
		x = floor(z);	
		dout[i] = ceil(z - x);
	end
end

// Plotting outputs
for (i=0; i<`binary_bits; i=i+1)
	    V(out[i]) <+ transition(dout[i]*vdd,0,0);
end

endmodule