Binary Counter Model Verilog-A

This article contains Verilog-A model for a binary counter, which counts up or down at the edge of the clock, when en is high.

Usage:

  1. Create a new cell in Library Manager named counter and select cell type Verilog A;
  2. Copy and paste the code provided;
  3. Specify bits variable to define the number of output bits;
  4. Specify start_code variable to be the start code of the counter;
  5. Specify count_up variable to be 1 for increasing or 0 for decresing counting;
  6. Specify step_size variable to be the step size of the counter (increment);
  7. Specify vth_clk variable to be threshold volatge of the clock signal;
  8. Specify vtol and ttol variables as signal and time tolerance to the clock signal;
  9. Specify vdd variable to be the output voltage of the counter;
  10. Specify t_edge and t_delay variables to be the rising/falling time and delay of the output waveform;
  11. Perform Check and Save;
  12. A cell symbol will be created;
  13. Instantiate counter cell into your design;
  14. Perform Check and Save and run the simulation.


Counter testbench

Counter testbench


Counter model simulation result

Counter model simulation result


Cell name: counter

Model type: Verilog-A

1    
2// Verilog-A model for Binary Counter
3// Source: AnalogHub.ie
4// Author: A. Sidun
5// Reference: A. Beckett
6
7`include "constants.vams"
8`include "disciplines.vams"
9`define bits 4
10
11module counter (clk,en,out);
12input clk, en;
13output [`bits-1 :0] out;
14electrical clk, en;
15electrical  [`bits-1 :0] out;
16
17parameter integer start_code = 0 from [0:(1<<`bits)-1];   // Start code for the counter
18parameter integer count_up = 1 from [0:1];         // Set 1 for increasing or 0 for decreasing
19parameter integer step_size = 1;              // Step size for the counter
20parameter real vth_clk = 0.5;               // Clock threshold
21parameter real vtol = 0;                  // Signal tolerance on the clk
22parameter real ttol = 0;                  // Time tolerance on the clk
23parameter real vdd = 1.0;
24parameter real vth = 1;
25parameter real vss = 0;
26parameter real t_delay = 30p;               // Delay time for the output waveform
27parameter real t_edge = 30p;               // Rising/falling times of the output waveform
28integer outval;                      // Internal counter 
29
30analog begin
31  @(initial_step("static","ac")) outval = start_code;
32  @(cross(V(clk)-vth_clk,1,vtol,ttol)) begin
33    if (V(en)<vth) outval=0.0;
34    else outval = (outval +(+count_up- !count_up)*step_size)%(1<<`bits);
35  end
36  generate j (`bits-1 , 0) begin
37    V(out[j]) <+ transition (!(!(outval &(1<,[object Object]