Comparator

This is a behavioral analog comparator that outputs VDD when the non-inverting input (inp) exceeds the inverting input (inn), and 0 V otherwise — ideal as a decision element in SAR ADC control logic, zero-crossing detectors, or overvoltage-protection circuits. t_delay models propagation delay and t_edge models rise/fall time, allowing you to approximate realistic comparator speed without a transistor-level model. The built-in $bound_step call prevents the simulator from stepping over fast transitions; comment it out if simulation speed is a concern and transitions are not critical. A typical use-case is the comparison stage in a SAR ADC behavioral model where the bit-cycling logic depends on clean, timely digital decisions from an analog subtraction.

This article contains Verilog-A model for a comparator.

Usage:

1. Create a new cell in Library Manager named comp and select cell type Verilog A;
2. Copy and paste the code provided;
3. Specify VDD variable to be the maximum output voltage of the comparator;
4. Specify t_edge and t_delay variables to be the rising/falling time and delay of the output waveform;
5. Perform Check and Save;
6. A cell symbol will be created;
7. Instantiate comp cell into your design;
8. Perform Check and Save and run the simulation.

Comparator testbench

Comparator simulation result

Cell name: comparator

Model type: Verilog-A