Comparator

This article contains Verilog-A model for a comparator.

Usage:

  1. Create a new cell in Library Manager named comp and select cell type Verilog A;
  2. Copy and paste the code provided;
  3. Specify VDD variable to be the maximum output voltage of the comparator;
  4. Specify t_edge and t_delay variables to be the rising/falling time and delay of the output waveform;
  5. Perform Check and Save;
  6. A cell symbol will be created;
  7. Instantiate comp cell into your design;
  8. Perform Check and Save and run the simulation.


Comparator testbench

Comparator testbench


Comparator simulation result

Comparator simulation result


Cell name: comparator

Model type: Verilog-A

1    
2// Comparator model
3// Author: A. Sidun
4// Source: AnalogHub.ie
5
6`include "constants.vams"
7`include "disciplines.vams"
8
9module comparator (inp, inn, out);
10    input inp, inn;
11    output out;
12    electrical inp, inn, out; 
13    parameter real VDD = 3.3; 			// Output voltage during high state
14    parameter real t_delay = 1e-9; 		// Propagation delay
15    parameter real t_edge = 100e-12; 		// Rise and fall times
16    
17    analog begin
18        V(out) <+ VDD * transition(V(inp) > V(inn), t_delay, t_edge);
19		$bound_step(1/(2*t_delay));  // comment this option if the sim is too slow
20    end
21endmodule