Pulse Width Modulated generator
This article contains Verilog-A models for a Pulse Width Modulated generator.
Usage:
- Create a new cell in Library Manager named pwm_gen_clk and select cell type Verilog A;
- Copy and paste the code provided;
- Specify vdd and vss variables to reflect high/low levels of the clk;
- Specify t_edge and t_delay variables to be the rising/falling time and delay of the output waveform;
- Specify period to define the input clock period;
- Specify duty to define the desired output duty cycle;
- Perform Check and Save;
- A cell symbol will be created;
- Instantiate pwm_gen_clk cell into your design;
- Perform Check and Save and run the simulation.
Pulse Width Modulated generator
Cell name: pwm_gen_clk
Model type: Verilog-A
1// PWM generator (fixed duty cycle, internal clock)
2// Author: A. Sidun
3// Source: AnalogHub.ie
4`include "constants.vams"
5`include "disciplines.vams"
6
7module pwm_gen_clk(vout,clk);
8output vout;
9input clk;
10electrical vout, clk;
11
12parameter real t_delay = 1e-9; //Output Waveform delay Time.
13parameter real vss = 0.0; //Zero Value used in Output Pulse Waveform.
14parameter real vdd = 1.0; //One Value used in Output Pulse Waveform.
15parameter real period = 1e-6; //Period of Input Waveform.
16parameter real t_edge = 1e-9;
17parameter real duty = 0.5 from (0.0:1.0); //Duty Factor for Output Pulse Waveform.
18
19
20integer trigger;
21real width; //Output Pulse Width (Duration of 'vdd').
22real period_1, duty_1, max_step;
23
24analog begin
25 @(initial_step) begin
26 max_step = min(t_edge, t_edge);
27 width = duty * (period - (t_edge + t_edge));
28 end //initial_step
29
30 $bound_step(max_step);
31 @(cross(V(clk) - vdd/2, +1)) begin
32 @( timer(t_delay, period) ) trigger = 1; //Generation of rising Edge
33 @( timer(t_delay+t_edge+width, period) ) trigger = 0; //Generation of falling Edge
34 end
35
36 V(vout) <+ vss + (vdd-vss) * transition(trigger, 0.0, t_edge, t_edge);
37end //analog
38
39endmodule