2 min readByAleksandr SidunAleksandr Sidun
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Pulse Width Modulated generator

This is a behavioral pulse-width modulation generator that produces a fixed-duty-cycle square wave phase-locked to an external input clock, intended for switching-converter testbenches, gate-driver stimulus sources, or any design requiring a precisely timed on-time. The external clock (clk) triggers the output; duty (0–1 exclusive) and period set the duty cycle and output period, while vdd/vss define the output swing and t_edge/t_delay control edge sharpness and phase offset. A typical use-case is supplying a PWM drive signal to a switch model in a DC-DC converter simulation where you need to sweep duty cycle independently of switching frequency. Note that period must match the input clock period for the timing to be consistent.

This article contains Verilog-A models for a Pulse Width Modulated generator.

Usage:

  1. Create a new cell in Library Manager named pwm_gen_clk and select cell type Verilog A;
  2. Copy and paste the code provided;
  3. Specify vdd and vss variables to reflect high/low levels of the clk;
  4. Specify t_edge and t_delay variables to be the rising/falling time and delay of the output waveform;
  5. Specify period to define the input clock period;
  6. Specify duty to define the desired output duty cycle;
  7. Perform Check and Save;
  8. A cell symbol will be created;
  9. Instantiate pwm_gen_clk cell into your design;
  10. Perform Check and Save and run the simulation.

Pulse Width Modulated generator

Cell name: pwm_gen_clk

Model type: Verilog-A

verilog
1// PWM generator (fixed duty cycle) 2`include "constants.vams" 3`include "disciplines.vams" 4 5module pwm_gen_clk(vout,clk); 6output vout; 7input clk; 8electrical vout, clk; 9 10//parameter real t_delay = 1e-9; //Output Waveform delay Time. 11parameter real vss = 0.0; //Zero Value used in Output Pulse Waveform. 12parameter real vdd = 1.0; //One Value used in Output Pulse Waveform. 13parameter real period = 1e-6; //Period of Input Waveform. 14parameter real t_edge = 1e-9; 15parameter real duty = 0.5 from (0.0:1.0); //Duty Factor for Output Pulse Waveform. 16 17 18integer trigger; 19real width; //Output Pulse Width (Duration of 'vdd'). 20real period_1, duty_1, max_step; 21 22analog begin 23 @(initial_step) begin 24 max_step = min(t_edge, t_edge); 25 width = duty * (period - (t_edge + t_edge)); 26 end //initial_step 27 28 $bound_step(max_step); 29 30 31@(cross( V(clk) - vdd/2, +1)) trigger = 1; //Generation of rising Edge 32@(cross( absdelay(V(clk) - vdd/2, width), +1)) trigger = 0; 33 34 35// $display("Falling trigger, %d", trigger); 36 //@( timer(t_delay, period) ) trigger = 1; //Generation of rising Edge 37 //@( timer(t_delay+t_edge+width, period) ) trigger = 0; //Generation of falling Edge 38 39 V(vout) <+ vss + (vdd-vss) * transition(trigger, 0.0, t_edge, t_edge); 40end //analog 41 42endmodule