Pulse Width Modulated generator

This article contains Verilog-A models for a Pulse Width Modulated generator.

Usage:

1. Create a new cell in Library Manager named pwm_gen_clk and select cell type Verilog A;
2. Copy and paste the code provided;
3. Specify vdd and vss variables to reflect high/low levels of the clk;
4. Specify t_edge and t_delay variables to be the rising/falling time and delay of the output waveform;
5. Specify period to define the input clock period;
6. Specify duty to define the desired output duty cycle;
7. Perform Check and Save;
8. A cell symbol will be created;
9. Instantiate pwm_gen_clk cell into your design;
10. Perform Check and Save and run the simulation.

Pulse Width Modulated generator

Cell name: pwm_gen_clk

Model type: Verilog-A

1 
2// PWM generator (fixed duty cycle, internal clock)
3// Author: A. Sidun
4// Source: AnalogHub.ie
5`include "constants.vams"
6`include "disciplines.vams"
7
8module pwm_gen_clk(vout,clk);
9output vout;
10input clk;
11electrical vout, clk;
12
13parameter real t_delay = 1e-9;      //Output Waveform delay Time.
14parameter real vss = 0.0;           //Zero Value used in Output Pulse Waveform.
15parameter real vdd = 1.0;           //One Value used in Output Pulse Waveform.
16parameter real period = 1e-6;       //Period of Input Waveform.
17parameter real t_edge = 1e-9;
18parameter real duty = 0.5 from (0.0:1.0); //Duty Factor for Output Pulse Waveform.
19
20
21integer trigger;
22real width; //Output Pulse Width (Duration of 'vdd').
23real period_1, duty_1, max_step;
24
25analog begin
26   @(initial_step) begin
27      max_step = min(t_edge, t_edge);
28      width = duty * (period - (t_edge + t_edge));
29   end //initial_step
30
31   $bound_step(max_step);
32   @(cross(V(clk) - vdd/2, +1)) begin
33      @( timer(t_delay, period) ) trigger = 1; //Generation of rising Edge
34      @( timer(t_delay+t_edge+width, period) ) trigger = 0; //Generation of falling Edge
35   end
36
37   V(vout) <+ vss + (vdd-vss) * transition(trigger, 0.0, t_edge, t_edge);
38end //analog
39
40endmodule