Analog-to-Digital (ADC) Verilog-A model

This article contains Verilog-A model for an Analog-to-Digital Converter (ADC).

Usage:

  1. Create a new cell in Library Manager named ADC and select cell type Verilog A;
  2. Copy and paste the code provided;
  3. Modify bits variable to define ADC resolution;
  4. Specify vmin and vmax variables to define the input signal swing;
  5. Specify vdd and vss variables to define output voltage levels;
  6. Specify tt and td variables to define rising/falling edge times and output signal delay;
  7. Specify dir variable to be +1 for rising and -1 for falling clock edge triggering;
  8. Perform Check and Save;
  9. A cell symbol will be created;
  10. Instantiate ADC cell into your design;
  11. Perform Check and Save and run the simulation.


ADC-DAC testbench

ADC-DAC testbench


ADC-DAC simulation result

ADC-DAC simulation result


Cell name: ADC

Model type: Verilog-A

1// N-bit Analog to Digital Converter
2// LSB is <0>
3// Change binary_bits variable for your needs!
4// Author: A. Sidun
5// Source: AnalogHub.ie
6
7`include "constants.vams"
8`include "disciplines.vams"
9`define bits 12					// define number of binary bits here
10module ADC (out, in, clk);
11    parameter real vmin = 0.0;			// minimum input voltage (V)
12    parameter real vmax = 1.0 from (vmin:inf);	// maximum input voltage (V)
13    parameter real td = 0 from [0:inf);		// delay from clock edge to output (s)
14    parameter real tt = 0 from [0:inf);		// transition time of output (s)
15    parameter real vdd = 5;			// voltage level of logic 1 (V)
16    parameter real vss = 0;			// voltage level of logic 0 (V)
17    parameter real thresh = (vdd+vss)/2;	// logic threshold level (V)
18    parameter integer dir = +1 from [-1:1] exclude 0;
19    						// 1 for trigger on rising edge
20						// -1 for falling
21    localparam integer levels = 1<<`bits;
22    input in, clk;
23    output [`bits-1:0] out;
24    voltage in, clk;
25    voltage [`bits-1:0] out;
26    integer result;
27    genvar i;
28
29    analog begin
30        @(cross(V(clk)-thresh, dir) or initial_step) begin
31	    result = levels*((V(in) - vmin))/(vmax - vmin);
32	    if (result > levels-1)
33	        result = levels-1;
34	    else if (result < 0)
35	        result = 0;
36	end
37
38	for (i=0; i<`bits; i=i+1)
39	    V(out[i]) <+ transition(result & (1<<i) ? vdd : vss, td, tt);
40    end
41endmodule